This invention relates to a monolithically integrated electronic device, as well as to a process for fabricating the same.
Specifically, the invention relates to an electronic device that is integrated monolithically in a semiconductor substrate and includes a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region, and having a first diffused region which extends continuously from the substrate surface to the buried region.
The invention also relates to a process for fabricating an electronic device, integrated monolithically in a semiconductor substrate and having a bipolar transistor connected in series to at least one MOS transistor, the process including forming a bipolar transistor base region consisting of a first buried region and a surface diffused region extending from the surface to the buried region.
As is well known, the expression xe2x80x9cemitter-switching configured electronic devicexe2x80x9d is used to indicate a circuit arrangement wherein a low-voltage (BJT or MOS) transistor is connected in series to a high-voltage bipolar transistor such that the low-voltage transistor will cut off the emitter current flow of the high-voltage transistor, thereby causing the device to be turned off.
The above arrangement combines the advantages of both transistor types, and allows extension of the power device utility to applications that would be impracticable using either transistor type alone.
An example of the above prior structure called a xe2x80x9ccascodexe2x80x9d is shown in FIG. 1.
A first epitaxial layer 1xe2x80x2 is grown on a substrate Sxe2x80x2 having a high concentration of an N-type dopant.
A first P-type buried region 2xe2x80x2, and a second N-type buried region 3xe2x80x2 overlying the first region 2xe2x80x2, are formed in this layer 1xe2x80x2 by ion implantation followed by a diffusion process.
These first and second regions are to form the deep base and emitter, respectively, of a high-voltage BJT transistor, designated B.
Thereafter, a second N-type epitaxial layer 4xe2x80x2 is grown over the first epitaxial layer 1xe2x80x2.
Regions 6xe2x80x2 of the P+ type are formed preferably in the surface of the second epitaxial layer 4xe2x80x2, as by ion implantation followed by a diffusing step.
These regions 6xe2x80x2 are caused to join the P-type buried regions in the first epitaxial layer 1xe2x80x2 in order to provide base surface contacts for transistor B.
Subsequently, regions 5xe2x80x2 of the N+ type are formed that will extend from the surface of the second epitaxial layer 4xe2x80x2 down to the periphery of the emitter region 3xe2x80x2.
An isolation layer is then formed selectively to provide a gate oxide layer 7xe2x80x2 for a pair of DMOSFET vertical transistors D.
By conventional deposition and photolithography techniques, a plurality of polycrystalline silicon regions 8xe2x80x2 are formed to provide gate electrodes for the DMOSFETs D.
By conventional photolithography and ion implantation techniques, first P-type regions 9xe2x80x2 and second N-type regions 10 are created in the monocrystalline silicon surface between the gate regions to respectively provide body and source regions for the DMOSFETs D.
By conventional photolithography and deposition techniques, electrical contacts 11xe2x80x2 and the associated electrodes are formed in the front surface of the silicon wafer.
While advantageous on several counts, this prior solution has some drawbacks.
The flow of the base current of transistor B, from the base region 6xe2x80x2 to the deep base region 2xe2x80x2, meets with steadily increasing resistance in going from a higher concentration layer 6xe2x80x2 to a lower concentration layer 2xe2x80x2 before entering the emitter region 3xe2x80x2. This situation produces a decreasing difference of potential from region 3 to region 2. In particular, this difference will be greatest in the peripheral area of the emitter region 3xe2x80x2 and least toward the middle of said region 3xe2x80x2.
The flow of the emitter/collector current will therefore concentrate in the peripheral area of the emitter region 3xe2x80x2.
This increased current flow causes the temperature to rise in that area, thereby enhancing the efficiency of the peripheral area of the emitter region and causing the current flow to increase further. Thus, a saturation effect is caused to occur, with a positive loop which deteriorates the overall structure performance.
The technical problem underlying this invention is to provide a cascode circuit structure, having a bipolar transistor and a MOS transistor, with structural and functional features appropriate to afford better control of the bipolar transistor current flow and overcome the limitations of prior circuit structures.
The disclosed embodiment of the present invention provides an electronic device having a bipolar transistor and a MOS transistor, wherein the base surface region of the bipolar transistor is surrounded by an isolation structure directed to isolate it from the associated emitter region.
In accordance with one embodiment of the invention, an electronic device is provided that includes a bipolar transistor connected in series to at least one MOS transistor integrated monolithically in a semiconductor substrate, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface to the buried region, the diffused region formed to be partially enclosed in an isolation trench region extending in the buried region.
In accordance with another embodiment of the invention, a monolithically integrated power device is disclosed, including a MOSFET transistor and a bipolar power transistor coupled together to form a cascode-type cell, the bipolar power transistor having a first buried region of a first type and a second buried region of a second type formed over the first buried region in a first epitaxial layer, a second epitaxial layer formed over the first epitaxial layer, a plurality of isolation trenches formed in the second epitaxial layer to extend from the surface of the second epitaxial layer through the second buried region and into the first buried region; and a plurality of diffused regions formed to be partially enclosed by the respective isolation trench and to contact the first buried region.
In accordance with yet another embodiment of the invention, a process for fabricating an electronic device is provided, including forming a bipolar transistor connected in series to at least one MOS transistor integrated monolithically in a semiconductor substrate, the process of forming including forming a base region of the bipolar transistor having a first buried region and a surface diffused region extending from the surface down to the buried region, and forming an isolation trench region extending down to and enclosing the diffused region filled in the buried region.
The features and advantages of a device according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.